Embodiments of the invention relate to a post package repair device, and more particularly to a technology for masking a rupture operation in case of a post package repair operation.
A Dynamic Random Access Memory (DRAM) includes a plurality of memory cells arranged in the form of a matrix. However, if a defective or failed cell occurs in at least one memory cell from among a plurality of memory cells, it is impossible for a semiconductor memory device to be normally operated, so that the semiconductor memory device having the defective cell is regarded as a defective product and abandoned. As the semiconductor memory device has been developed to have a higher degree of integration at a higher speed, there is a higher possibility of causing defective cells.
As a result, a production yield denoted by the ratio of a total number of chips to the number of normal chips, which is needed for deciding production costs of DRAMs, is gradually reduced. Therefore, in order to increase a production yield of semiconductor memory devices, many developers and companies are conducting intensive research into a method for fabricating highly-integrated semiconductor memory devices configured to operate at a higher speed and a method for efficiently repairing defective cells.
A method for repairing a defective cell of DRAMs is classified into a method (hereinafter referred to as a wafer repair method) for repairing the defective cell in a wafer state and a method (hereinafter referred to as a packaging repair method) for repairing the defective cell in a packaging state.
In this case, the wafer repairing method performs testing of memory cells of the semiconductor memory device at a wafer level, and replaces a defective cell with a redundancy cell. The packaging repair method performs testing of memory cells of the semiconductor memory device at a package state, and replaces a defective cell with a redundancy cell at the package state. The above-mentioned case in which repairing of the defective cell is performed at a package state is referred to as a Post Package Repair (PPR) method.
However, according to a circuit structure capable of being simultaneously replaced with redundancy word lines of two banks during a post package repair (PPR) operation, fuse resources can be simultaneously reduced. In addition, it is impossible to recognize the presence or absence of the remaining fuses available to the PPR operation. In addition, it is impossible for the fuse structure allocated to each independent bank to maximally use a plurality of fuses, and the rupture operation can be repeatedly performed irrespective of the remaining fuses during the PPR operation.